1. Field of the Invention
The present invention generally relates to a cell search method and apparatus for the code division multiple access (CDMA) system, and more particularly to a cell search method and apparatus for the wideband code division multiple access (W-CDMA) system to reduce the effect of clock offset.
2. Description of the Related Art
CDMA cellular systems based on code division multiple access (CDMA) using a direct sequence spread spectrum (DSSS) technology greatly increases the channel capacity. These systems are receiving much attention in the recent work on ground mobile communication systems. In general, bandwidth efficiency of a CDMA system is much better than that of other multiple access systems (FDMA, TDMA) because of the universal frequency reuse property. Moreover, the cell planning is also easy in these systems. Hence, a CDMA cellular system can be a promising system in the future.
Third generation partnership project (3GPP) wideband code division multiple access/frequency division duplex system (W-CDMA/FDD) has been adopted as one of the standards for the IMT-2000 third generation system. In CDMA cellular systems, the procedure used by a user equipment (UE) to search for the best cell is referred to as “cell search”. Fast cell search is very important in order to reduce the UE switched-on delay (initial search), to increase standby time (idle mode search) and to maintain good link quality during handover (active mode search).
U.S. Pat. No. 6,038,250 issued to Shou et al., entitled “Initial Synchronization Method And Receiver for DS-CDMA Inter Base Station Asynchronous Cellular System”, discloses that cells are searched at a high speed using an initial synchronization method and a receiver for a DS-CDMA inter base station asynchronous cellular system. A base band received signal is input to a matched filter and is correlated with a spread code supplied from a spread code generator. A signal electric power calculator calculates the electric power of the correlation output of the matched filter, and outputs the result to a long code synchronization timing determiner, a threshold value calculator, and a long code identifier. During the initial cell search, the spread code generator outputs a short code that is common to the control channel of each of the base stations. After the long code synchronization timing has been determined, each of the segments of the N chips which constituting a portion of the synthesized spread code sequence is sequentially replaced and output.
U.S. Pat. No. 6,185,244 issued to Nystrom et al., entitled “Cell searching in a CDMA communications system” discloses a coding scheme for more effectively acquiring a long code and frame timing during a cell search in a CDMA communications system. A code set of length M Q-ary code words including symbols from a set of Q short codes is defined with certain properties. The primary property to be satisfied is that no cyclic shift of a code word yields a valid code word. The other properties to be satisfied are that there is a one-to-one mapping between a long code message and a valid code word, and a decoder should be able to find both the random shift (thereby implicitly finding the frame timing) and the transmitted code word (i.e., its associated long code indication message) in the presence of interference and noise, with some degree of accuracy and reasonable complexity.
U.S. Pat. No. 6,289,007 issued to Kim et al., entitled “Method for Acquiring A Cell Site Station in Asynchronous CDMA Cellular Communication Systems”, discloses that a group code and a cell code are multiplexed and then used as a pilot code for discriminating a base station in asynchronous cellular CDMA (Code Division Multiple Access) communication systems. Using the multiplexed code, interferences are reduced in case of using two pilot codes. A method for acquiring a cell site station in asynchronous CDMA (Code Division Multiple Access) communication systems including a base station controller, a plurality of mobile stations and base stations, and discriminating the base stations by using different sequences, the method including the steps of: a) assigning a group code of the cell as a pilot code of an inphase channel of the base stations; b) assigning a cell code of the cell as a pilot code of a quadrature channel of the base stations; and c) multiplexing the pilot codes of inphase channel and the quadrature channel, and generating an inphase/quadrature pilot code.
Now referring to FIG. 1, it will be helpful to understand the simplified frame structure of the 3GPP W-CDMA/FDD system. First, in 3GPP W-CDMA/FDD system, the cell search is typically carried out in three stages by employing two peculiarly designed synchronization channels and a common pilot channel. In the first stage 110, a primary synchronization channel (PSCH) 111 is used for slot synchronization. The primary synchronization channel (PSCH) 111 consists of a primary synchronization code which is denoted acp, where “a” (=±1) depends on the existence of the transmit diversity at the base station (BS). In the second stage 120, the secondary synchronization channel (SSCH) 121 is used for frame/code group identification. The secondary synchronization channel (SSCH) 121 consists of the secondary synchronization code, which is denoted by acs, and the coefficient of cs is similar to that in PSCH. In the third stage 130, a common pilot channel (CPICH) 131 is used for determination of the downlink scrambling code. As shown, the 10-ms frame consists of 15 slots, and the system uses the chip rate of 3.84 Mchips/sec. Eventually, there are 38400 chips in a frame and 2560 chips in a slot. In addition, PSCH and SSCH are 256-chip long and only transmitted at the beginning of the slot boundaries.
Conventional cell search processes for the 3GPP W-CDMA/FDD system can be divided into two broad categories: the serial search and the pipeline search processes.
As shown in FIG. 2, the serial search process needs to go through all the three stages of synchronization one by one before a new three-stage attempt can commence: (1) slot synchronization, (2) frame synchronization/code group identification, (3) scrambling code identification. Now referring to FIG. 2, it is a simplified diagram for the conventional three-stage serial cell search processes. For convenience, a complete three-stage cell search procedure will be referred as a trial. Trials are not overlapped in the serial search, and trials are repeated again and again until the search succeeds. Namely, only one stage works at a time, e.g. only a block 211, a block 212 and a block 213 works at a time (here, a block means as a stage of a trial), which implies lower power consumption, but at the expense of a longer search time.
On the other hand, referring to FIG. 3, it is a simplified diagram for the conventional three-stage pipeline search processes. In the pipeline search processes, three stages are performed concurrently, which means the trials are overlapped. Namely, a block 311  a block 321 and a block 331 are in the same trial. Obviously, in the pipeline search processes, more trials are possible for a fixed amount of time, and hence result in a faster search. Of course, they require more power consuming. Note that no extra hardware is needed for the pipeline search processes, as compared with the serial search. For simplicity, we assume 10 (ms) is required for each stage, and then (K+2)×10 (ms) of the total processing time is necessary for a successful search which is terminated in the Kth trial.
However, a common assumption was usually made in the above prior art for the cell search, that is, the chip clock of the transmitter is known precisely to the receiver (namely, no clock offset), the frequency of incoming signal is assumed without frequency offset. In practice, the frequency offset is due to the source of frequency instability of the crystal oscillators of the user equipment, namely, the frequency of incoming signal will be with frequency offset for the user equipment. Frequency offset in baseband causes two effects (1) phase rotation (2) clock offset, wherein the effect of clock offset is not taken into account in past. The clock offset resulted from the frequency offset exists between the basestation and user equipment. The chip clock offset may make the error information and increase the cell search time. FIG. 4a and FIG. 4b are not prior arts, but the observations of clock drifts at the output of a primary code matched filter under the effect of clock offset by the inventors. As shown in FIG. 4a and FIG. 4b, the signal level degrades and the inter-chip interference increases significantly under the effect of chip clock offset.